1. Field of the Invention
The present invention relates to dual supply off chip driver circuits, and in particular to tri-state delay boost circuitry.
2. Background of the Invention
When driving off chip, there are three valid states: logic 0; logic 1; and tri-state. Tri-state means the driver in question is not driving a logic 0 or logic 1. The term tri-state can be used to describe the state of a particular driver connected to a bus. In addition, a driver that is in tri-state (as opposed to logic 0 or logic 1) is analogous to being in a stand-by mode.
FIGS. 1 and 2 illustrate prior art applications of tri-state circuitry. A typical dual supply driver circuit 10 is illustrated in FIG. 1. As used herein, the driver is the portion of an input/output (I/O) sending signals off a chip. The driver is connected to the bus and drives signals onto the bus. The tri-state portion 12 of circuit 10 is used to create and manipulate signal EN2 (depending on input values at pins TS and D1), which are further manipulated to signal the driver to turn on or off. When the driver is tri-stated, it is electrically disconnected from the bus.
In addition to signal EN2, signal A2 is also provided based on an input value at pin A.A2 provides a logic 0 or logic 1 value to an output stage 14 (node G1 or G2, which in turn sends, the logic value to PAD). The value at PAD is sent from the chip when the driver is on.
In determining the signals that go to output stage 14 and ultimately PAD, signals EN2 and A2 are processed through a pre-drive stage 16 having circuitry that includes a NAND gate 18 and a NOR gate 20. In FIGS. 1 and 2, signals EN2 and A2 are processed through NAND gate 18, and signals EN2BAR (inverse of signal EN2) and A2 are processed through NOR gate 20. FIG. 2 illustrates a circuit 24, which includes a typical NAND/NOR predriver (as illustrated in the FIG. 1 schematic).
In a prior art NAND/NOR driver as in FIGS. 1 and 2, the tri-state signal delay (i.e., time it takes for a signal generated from input values at pins TS and D1 to travel to PAD) is greater than the driver critical path delay (i.e., time it takes for a signal generated by the input value at pin A to travel to PAD). The tri-state signal experiences a longer delay because it must travel through an additional stage of logic (NAND gate 212 at tri-state portion 12) as compared to the input value at pin A. As a result, in most I/O""s, turning a bus on/off or tri-stating the bus, inherently takes longer than switching from a logic 0 to logic 1 or logic 1 to logic 0.
Many applications require tri-state delays that are equivalent to driver critical path delay. Such a requirement is even more important with zero-bus-turnaround applications where the driver is tri-stated and the receiver enabled or the receiver disabled and driver enabled all in the same cycle. Additionally, the Peripheral Component Interconnect and Peripheral Component Interconnect Extended (PCI/PCIX) specification imposes output signal slew rate restrictions thereby making it more difficult to achieve a tri-state delay equivalent to the critical path delay when interfacing a particular chip to a PCI/PCI-X bus.
One aspect of the present invention is a driver for driving output to a pad including boost circuitry for reducing tri-state delay. The driver includes at least one NAND gate predriver circuit, at least one NOR gate predriver circuit, at least one first boost leg for providing a boost current to each of the at least one NAND gate predriver circuit during turn on of each of the NAND gate predriver circuits, and at least one second boost leg for providing a boost current to each of the at least one NOR gate predriver circuits during turn on of each of the NOR gate predriver circuits.
Another aspect of the present invention is a method of decreasing the time it takes for a tri-state signal to travel to a pad. The method includes the steps of providing at least one NAND gate predriver circuit, providing at least one NOR gate predriver circuit, providing at least one output node in communication with the at least one NAND gate predriver circuit, the at least one NOR gate predriver circuit, and the pad, providing at least one boost leg each having at least one subcircuit with a first end and a second end, the second end in communication with the at least one NAND gate predriver circuit and the at least one NOR gate predriver circuit, providing at least one first input for providing a first signal to each of the predriver circuits, providing at least one enable signal from a tri-state circuit, the at least one enable signal for providing either on enable signals or off enable signals to each of the predriver circuits and each of the at least one boost leg first ends, the on enable signals turning on said predriver circuits and the off enable signals turning off the predriver circuits, and allowing at least one of the at least one output node to discharge or charge upon receipt of the on or off enable signal by the at least one boost leg.